ASPLOS XI Tutorial Call for Participation:
Software Instrumentation as a Tool for Architecture and Compiler Research

Saturday, October 9, 2004
Boston, Massachusetts

 

Abstract:

 

This tutorial describes a software instrumentation tool called Pin (http://www.pintool.org). Pin is an ATOM-like instrumentation tool for Linux* executables and is provided by Intel®. Unlike static instrumentation tools, it allows code (written in C or C++) to be injected at arbitrary places in an executable while it is running. The injected code is used to observe the behavior of the program, and can be used to write branch predictors, profilers, memory leak detectors, etc. Its robust design and simple user model makes it easy to do studies that span workstation applications to complex server applications like commercial databases. Currently supported platforms include the Intel® Xscale ™, IA-32, EM64T (IA-32 64 bit extension), and Itanium® microprocessors.

 

The emphasis of this tutorial is on using Pin for architecture and compiler research and education. It is fast and easy to model microarchitectural features in Pin. For example, a simple data cache model is only 1 page of C code. Instrumentation is typically much faster than simulation, so it is possible to run entire benchmarks to completion and to try programs that are difficult to run on a detailed performance model. For compiler research, Pin is useful for profiling for the specific conditions where an optimization may apply. For example, a simple pintool can determine if a memory instruction has a striding reference pattern. Pin makes it possible to answer what-if questions easily and establish the limits of the benefit for a particular optimization. After using instrumentation for initial feasibility studies, then the researcher can implement their ideas in a detailed performance model or a compiler.

 

The first session begins with an introduction to the API and basic concepts for writing instrumentation tools. With the recent release of Pin 2 for Xscale and IA-32, the API has been revamped to make it possible to write architecture independent tools. The presentation highlights the changes.  Session 1 concludes with instruction on how to write instrumentation tools that are useful for architecture and compiler studies. The second session consists of presentations on research projects that use Pin. This includes program phase analysis for instruction trace collection, instruction prefetching, data race detection in parallel programs, and dynamic optimization.

 

Session 1 (1:30-3:30PM): Introduction to writing Pintools

1:30 Introduction to Pin API CK Luk, Intel

2:30 Instrumentation tools for architecture and compiler research Dan Connors, University of Colorado

 

3:30 Break

 

Session 2 (4-6PM): Research Projects Using Pin

4:00 Instruction Prefetching and Efficient Micro-architecture Simulations Wei-Chung Hsu, University of Minnesota

Wei will present a framework that combines the Pin tool and the Pfmon library to support dynamic instruction cache prefetching and efficient micro-architecture simulations.

4:30 The PinPoints toolkit for finding/simulating representative regions of large programs with PIN Harish Patil, Intel

5:00 Software Quality Tools using Pin Tipp Moseley, University of Colorado and Intel

Tipp will present the Linux Inter-Process Race Analyzer (LIRA), a Pin tool that checks for race conditions and potential deadlock on both memory and files in shared-memory multi-process applications such as Oracle, PostgreSQL, or Apache.

5:30 Rogue: Dynamic Optimization Vijay Janapa Reddi, University of Colorado and Intel

Vijay will present a new dynamic optimization framework for Pin. The optimizer has an open API, so users can develop custom optimizations without having to create their own infrastructure. He will discuss the ROGUE system (Runtime Optimizations Guided Using Edges), an optimizer built on the API.

Presenter information:

 

Robert Cohn is a Principal Engineer at Intel, where he works on just in time compilation, dynamic instrumentation, and post link optimization in Spike/Pin project. Previously, he worked for Digital and Compaq where he implemented profile guided optimization in the product compiler and Om post link optimizer for Alpha. He was a lead developer for the Spike post link optimizer. Robert received a Ph.D. in Computer Science from Carnegie Mellon in 1992.

 

Dan Connors (http://www.cs.colorado.edu/~dconnors) Dan Connors is an assistant Professor at the University of Colorado at Boulder.  He received his Ph.D. in Computer Engineering from the University of Illinois at Urbana-Champaign in 2000.  His main research area is computer architecture, and his interests span compilers,

operating systems, and microarchitecture technologies.  He is the director of the DRACO project, which explores run-time optimization technologies that enable multi threaded multi-core microprocessor designs.

  

Wei-Chung Hsu (http://www-users.cs.umn.edu/~hsu/) Wei Hsu is an associate professor in the department of computer science and engineering, at the University of Minnesota, where he works on the Adore runtime optimization system. Previously, he was a runtime optimization architect at the Hewlett Packard Company. Prior to joining HP, he was a senior architect at Cray Research.  Wei received his PhD degree in computer science from the University of Wisconsin, Madison, in 1987.

 

Chi-Keung (C-K) Luk is a Staff Engineer at the Intel Massachusetts Microprocessor Design Center, where he currently works on the Spike/Pin project.  His research interests include memory system performance, compiler optimization, binary translation, and performance monitoring. He received his PhD from the University of Toronto and was a visiting scholar at Carnegie Mellon University. His dissertation titled "Optimizing the Cache Performance of Non-Numeric Applications" was nominated for the ACM Doctoral Dissertation Award in 2000. He has published numerous papers at top conferences and journals and filed several patent applications. He served on the program committees of the 34th MICRO and the First ACM Workshop on Memory System Performance.

 

Tipp Moseley (http://home.cs.colorado.edu/~moseleyt)

 

Harish Patil (http://www.cs.wisc.edu/~patil) is a Senior Systems Engineer at Intel, where he works on the Spike/Pin project. His current interests include workload characterization and simulation of parallel programs. He received his Ph.D. in Compilers and Programming Languages from University of Wisconsin, Madison in 1996. He then worked with Hewlett Packard's Massachusetts Language Lab for two years mainly doing research in debugging of optimized code. He later joined Compaq where he worked on Spike, a simulation framework [ASIM], static branch prediction, and SPEC performance.

 

Vijay Janapa Reddi (http://eces.colorado.edu/~janapare)

 

 

 

 

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